1. Field of the Invention
The present invention relates to a solid-state image sensor, and particularly relates to a two-dimensional solid-state image sensor characterized by the reading of signals.
2. Description of the Prior Art
Generally, a solid-state image sensor comprises photo sensors and a scanning circuit on a semiconductor material such as silicon, and if suitable photo sensors are selected, images from the visible region to an infrared region can be provided. As compared with a conventional image tube, a solid-state image sensor is advantageous in that it is compact, light in weight and has high reliability and in particular, few portions need to be adjusted in manufacturing a camera using such an image sensor. Thus, such a solid-state image sensor has recently attracted attention in various fields.
As a scanning circuit of a solid-state image sensor, a MOS switch system or a CCD (charge coupled device) system is conventionally used in most cases. In the former MOS switch system, spike noise due to the MOS switches used for reading the signals is mixed into the signals, which decreases the signal-to-noise ratio. In addition, the spike noise differs between the columns for reading the signals, which generates a so called fixed pattern noise to further decrease the signal-to-noise ratio, and as a result, a MOS switch system cannot be used for the detection of an extremely low light level application which requires a high signal-to-noise ratio. On the other hand, in the latter CCD system, particularly in a CCD interline system which has been widely used recently because it is capable of freely selecting photo sensors as in a MOS system, CCDs are disposed between the respective columns of photo sensors, and in order to enlarge the effective area of the photo sensors, it is desired to minimize the area of the CCD portion in making a design. In addition, the charge transferring capacity of the CCDs is proportional to the storage gate area for one stage of CCDs if the CCDs have the same structure. Accordingly, if the area of the CCD portion is decreased, the maximum value of the charge to be handled becomes limited. Such a problem becomes serious particularly at the time of detecting a low level signal in a high level background as in an infrared ray solid-state image sensor.
On the other hand, a solid-state image sensor generating less noise and having a high dynamic range has been proposed in which the respective vertical charge transferring elements are driven as a single potential well. For example, such a solid-state image sensor is shown in copending application of the same applicant as the present U.S. application Ser. No. 519,904, filed Aug. 3, 1983 (German application No. P3329095.4, filed Aug. 11, 1984) incorporated herein by reference. FIGS. 1 to 3 are drawings for explaining an operation of one example of such a solid-state image sensor.
FIG. 1 is a block diagram showing an example of the above described solid-state image sensor. An array of 3 columns.times.4 rows is represented for the purpose of facilitating the explanation. A solid-state image sensor comprises photo sensors 111 to 114, 211 to 214 and 311 to 314 disposed two-dimensionally on a semiconductor substrate, transfer gates 121 to 124, 221 to 224 and 321 to 324 formed of MOS transistors on the semiconductor substrate, vertical charge transferring elements 130, 230 and 330 formed on the semiconductor substrate, interface portions 140, 240 and 340 formed on the semiconductor substrate, which constitute an interface with a horizontal CCD 500, an output preamplifier 600 and an output portion 700. The solid-state image sensor further comprises a clock signal source 800 for applying clock signals, as described subsequently, to the vertical charge transferring elements 130, 230 and 330.
With reference to FIGS. 2A, 2B and 3, a structure and an operation of the portions relating to transfer of charge in a vertical direction, that is, vertical charge transferring elements 130 to 330 and interface portions 140 to 340, will be described in the following. FIG. 2A is a sectional view taken along the line II--II in FIG. 1; FIG. 2B shows the potential states in the portions shown in FIG. 2A; FIG. 3 is a timing chart of clock signals applied to the portions shown in FIG. 2A. The vertical charge transferring element 130 comprises four gate electrodes 131 to 134 and the interface portion 140 comprises two gate electrodes 141 and 142, the end of the interface portion 140 being in contact with a gate electrode 501 in the horizontal CCD 500. The reference numeral 10 denotes a semiconductor substrate. Channels are formed under the respective gate electrodes. These channels may be surface channels or buried channels. FIG. 2A shows a structure in which gaps are provided between the respective electrodes. However, multilayer gate electrodes may be used with overlapped portions between the electrodes. To the gate electrodes 131 to 134, 141 and 142, clock signals .phi..sub.V1 to .phi..sub.V4, .phi..sub.S and .phi..sub.T from the clock source 800 are applied respectively as shown in FIG. 3. In this case, n-channels are adopted. In the case of p-channels, the polarity of the clock signals will have to be inverted.
Vertical charge transfer in the portions shown in FIG. 2A will be described referring to FIG. 2B. The potential states S1 to S9 in FIG. 2B correspond respectively to the timings t1 to t9 in FIG. 3. For example, the state S1 is a potential state in the portions shown in FIG. 2A when it corresponds to the timing t1. At this time, the clock signals .phi..sub.V1 to .phi..sub.V4 are all at the level "H" and as a result, a large potential well is formed under the gate electrodes 131 to 134, and a deeper potential well is formed under the gate electrode 141 since the clock signal .phi..sub.S is at the level "H" higher than the clock signals .phi..sub.V1 to .phi..sub.V4, and a shallow potential barrier is formed under the gate electrode 142 since the clock signal .phi..sub.T is at the level "L". On the other hand, the horizontal CCD 500 performs charge transfer in the above described state and is in a potential state which changes in a reciprocating manner between the limits shown by the dotted lines in FIG. 2B. In such a state, when an arbitrary transfer gate in the vertical direction, for example a transfer gate 121, is turned on to read the content of the photo sensor 111 into the vertical charge transferring element 130, a signal charge Q.sub.S is given to the potential well under the gate electrodes 131 to 134. Then, in the timing t2, when the clock signal .phi..sub.V1 changes to be at the level "L", the signal charge Q.sub.S is pushed toward the direction of an arrow A in FIG. 2B, since the potential well under the gate electrode 131 becomes shallow as shown in the state S2. Further, in the timings t3 to t5, the clock signals .phi..sub.V2 to .phi..sub.V4 are successively brought to the level "L", the potential wells under the gate electrodes 132 to 134 become shallow successively as shown in the states S3 to S5, so that the signal charge Q.sub.S is pushed toward the direction of the arrow A. At the time when the clock signal .phi..sub.V4 is at the level "L", the signal charge Q.sub.S is stored in the potential well under the gate electrode 141. The gate electrode 141 must be sufficiently large for storing the signal charge Q.sub.S, but the potential well under the gate electrode 141 at the time when the clock signal .phi..sub.S is at the level "H" need not be deeper than the potential well under the gate electrodes 131 to 134 as shown in the above described example. Thus, the signal charge Q.sub.S is collected in the gate electrode 141 and after scanning is completed for one horizontal line in the horizontal CCD 500, the clock signal .phi..sub.H of the gate electrode 501 of the horizontal CCD 500 in contact with the gate electrode 142 is brought to the level "H" and the clock signal .phi..sub.T of the gate electrode 142 is brought to the level "H" in the timing t6. Then, the potentials under the respective gate electrodes become to be in the state S6 shown in FIG. 2B. At this time, the potential well under the gate electrode 142 is made shallower than the potential wells under the gate electrodes 141 and 501, but it is not necessarily needed to determine the potentials in such a manner. Next, in the timing t7, the clock signal .phi..sub.S is at the level "L" and the potential well under the gate electrode 141 becomes shallow as shown in the state S7, so that the signal charge Q.sub.S moves into the potential well under the gate electrode 501. After that, in the timing t8, clock signal .phi..sub.T is brought to the level "L" and the potential well under the gate electrode 142 becomes shallow as shown in the state S8, so that the signal charge Q.sub.S is transferred to the horizontal CCD 500. The horizontal CCD 500 which has received the signal charge Q.sub.S operates to transfer signals successively to the output preamplifier 600. After a signal is transferred to the horizontal CCD 500, the clock signals .phi..sub.V1 to .phi..sub.V4 and .phi..sub.S attain again the level "H" in the timing t9 and the same state as in the timing t1 is established.
Next, when a clock signal .phi..sub.T2 reaches the level "H", the transfer gate 122 is turned on to apply the signal of the photo sensor 112 to the vertical charge transferring element 130, so that the signal is transferred to the horizontal CCD 500 in the same operation as described above. Further, the same cycle is repeated so as to read the signals of the photo sensors 113 and 114, and thus one frame is brought to an end.
The above described operation is performed simultaneously in the other columns. Thus, scanning of a two-dimensional array is performed.
In accordance with the above described solid-state image sensor, since signal charge is transferred through the potential well in the same manner as in a conventional CCD system, spike noise as in an MOS system is never produced and the signal charge amount to be handled can be made extremely large since it is determined by the potential well in a whole vertical line of the vertical charge transferring elements 130, 230 and 330. In addition, even if the width of channels for forming a vertical signal line is made small in the vertical charge transferring elements, the signal charge amount to be handled can be made sufficiently large. Furthermore, since the interface portions 140, 240 and 340 and the horizontal CCD 500 can be formed outside the array of the photo sensors 111 to 114, 211 to 214 and 311 to 314, less limitation is made to the sizes thereof and it becomes easy to enlarge the interface portions and the horizontal CCD according to the necessary charge amount. In the above described solid-state image sensor, the vertical charge transferring elements are scanned in one horizontal period (conventionally, vertical charge transferring elements are scanned in a period nearly equivalent to the time of one frame at the maximum) and the time required for the signal charge Q.sub.S to exist in the channel is shortened, and as a result, channel leak current and the smear phenomenon can be reduced.
Meanwhile, a model of transfer of free charge has been considered as a mechanism of transfer of charge in the above described vertical charge transferring elements, which includes three processes, that is, thermal diffusion of charge by heat, self-induced drift and fringing field drift. Of these processes, the self-induced drift and fringing field drift are very important, and, particularly, the self-induced drift is caused, at an earlier time of transfer, by repulsion between the respective carriers. Most of the signal charges are transferred by the self-induced drift. Since carriers are distributed in a widespread manner in a channel under a gate electrode in the above described charge transferring elements, the effect of the above described self-induced drift is quite small and hence sufficient efficiency of transfer can not be obtained.